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IS62LV12816BLL
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
* High-speed access time: 55, 70, 100 ns * CMOS low power operation - 120 mW (typical) operating - 6 W (typical) CMOS standby * TTL compatible interface levels * Single 2.7V-3.45V VCC power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * Available in the 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm)
ISSI
DESCRIPTION
(R)
FEBRUARY 2001
The ISSI IS62LV12816BLL is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected) or when CE is low and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816BLL is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB CONTROL CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
1
IS62LV12816BLL
PIN CONFIGURATIONS 44-Pin TSOP (Type II)
1
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
ISSI
48-Pin mini BGA
2 3 4 5 6
(R)
A B C D E F G H
LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
N/C I/O0 I/O2 Vcc GND I/O6 I/O7 NC
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CE OE WE Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input LB UB NC Vcc GND Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
TRUTH TABLE
Mode Not Selected Output Disabled Read WE X X H X H H H L L L CE H L L L L L L L L L OE X X H X L L L X X X LB X H X H L H L L H L UB X H X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB1, ISB2 ISB1, ISB2 ICC ISB ICC
Write
ICC
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
IS62LV12816BLL
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V - 3.45V 2.7V - 3.45V
ISSI
(R)
1 2
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TBIAS VCC TSTG PT
(1)
Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc Related to GND Storage Temperature Power Dissipation
Value -0.5 to Vcc+0.5 -40 to +85 -0.3 to +3.6 -65 to +150 1.0
Unit V C V C W
3 4 5 6
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -1 mA VCC = Min., IOL = 2.1 mA Min. 2.0 -- 2.2 -0.2 -1 -1 Max. -- 0.4 VCC + 0.2 0.4 1 1 Unit V V V V A A
7 8 9 10
Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
11 12
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
3
IS62LV12816BLL
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.3V See Figures 1 and 2
ISSI
(R)
AC TEST LOADS
3070 3.0V
3070 3.0V
OUTPUT 30 pF Including jig and scope 3150
OUTPUT 5 pF Including jig and scope 3150
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
IS62LV12816BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC Vcc Dynamic Operating Supply Current ISB1 TTL Standby Current (TTL Inputs) OR ULB Control VCC = Max., VIN = VIH or VIL CE = VIL, f = 0, UB = VIH, LB = VIH VCC = Max., CE VCC - 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 Com. Ind. -- -- 5 5 -- -- 5 5 -- -- 5 5 Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH , f = 0 -55 Min. Max. -- 40 -- 45 -- 0.4 -- 1.0 -70 Min. Max. -- 30 -- 35 -- 0.4 -- 1.0
ISSI
Com. Ind. Com. Ind. -100 Min. Max. -- 20 -- 25 -- 0.4 -- 1.0 Unit mA mA
(R)
1 2 3
ISB2
CMOS Standby Current (CMOS Inputs)
A
4 5 6 7
OR ULB Control VCC = Max., CE = VIL VIN 0.2V, f = 0; UB / LB = VCC - 0.2V
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
(2) (2)
-55 Min. Max. 55 -- 10 -- -- -- 5 0 10 -- 0 0 -- 55 -- 55 30 20 -- 20 -- 55 25 --
-70 Min. Max. 70 -- 10 -- -- -- 5 0 10 -- 0 0 -- 70 -- 70 35 25 -- 25 -- 70 25 --
-100 Min. Max. 100 -- 15 -- -- -- 5 0 10 -- 0 0 -- 100 -- 100 50 30 -- 30 -- 100 35 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE tHZCE tBA tHZB tLZB
8 9 10 11 12
tLZCE(2)
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
5
IS62LV12816BLL
ISSI
(R)
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
IS62LV12816BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output -55 Min. Max. 55 50 50 0 0 45 45 25 0 -- 5 -- -- -- -- -- -- -- -- -- 30 -- -70 Min. Max. 70 65 65 0 0 60 60 30 0 -- 5 -- -- -- -- -- -- -- -- -- 30 --
ISSI
-100 Min. Max. 100 80 80 0 0 80 80 40 0 -- 5 -- -- -- -- -- -- -- -- -- 40 -- Unit ns ns ns ns ns ns ns ns ns ns ns
(R)
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE(3) tLZWE
(3)
1 2 3 4 5 6 7
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.3V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
VALID ADDRESS
t SA
CE
t SCS
t HA
8 9 10
WE
t AW t PWE1 t PWE2 t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
11
t HD
DATAIN VALID
UB_CSWR1.eps
t SD
DIN
12
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
7
IS62LV12816BLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
ISSI
t HA
(R)
OE
CE
LOW
t AW t PWE1
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CSWR2.eps
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS OE CE
VALID ADDRESS
LOW
t HA
LOW
t AW t PWE2
WE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CSWR3.eps
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
IS62LV12816BLL
WRITE CYCLE NO. 4 (UB/LB Controlled)
t WC
ADDRESS
ADDRESS 1
ISSI
t WC
ADDRESS 2
(R)
1 2
OE
t SA
CE
LOW
WE
t HA t SA t PBW t PBW
WORD 2
t HA
3 4
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
5
UB_CSWR4.eps
6 7
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc = 2.0V, CE * Vcc - 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.5 -- 0 Max. 3.45 5 -- -- Unit V A ns ns
VDR
IDR
8 9 10
tSDR tRDR
tRC
DATA RETENTION WAVEFORM (CE Controlled)
tSDR VCC 2.3V Data Retention Mode tRDR
11
CE VCC 0.2V
2.0V
VDR
12
CE GND
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01
9
IS62LV12816BLL
ISSI
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 55 70 100 Order Part No. Package IS62LV12816BLL-55T TSOP (Type II) IS62LV12816BLL-55B Mini BGA (6mm x 8mm) IS62LV12816BLL-70T TSOP (Type II) IS62LV12816BLL-70B Mini BGA (6mm x 8mm) IS62LV12816BLL-10T TSOP (Type II) IS62LV12816BLL-10B Mini BGA (6mm x 8mm)
Industrial Range: -40C to +85C
Speed (ns) 55 70 100 Order Part No. Package IS62LV12816BLL-55TI TSOP (Type II) IS62LV12816BLL-55BI Mini BGA (6mm x 8mm) IS62LV12816BLL-70TI TSOP (Type II) IS62LV12816BLL-70BI Mini BGA (6mm x 8mm) IS62LV12816BLL-10TI TSOP (Type II) IS62LV12816BLL-10BI Mini BGA (6mm x 8mm)
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 03/07/01

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